1. Field of the Invention
The present invention relates to a semiconductor storage device, more specifically to a technology for improving retention characteristics of data “1” and “0” in DRAM.
2. Description of the Related Art
In recent years, an increasingly higher integration is demanded in, particularly, an embedded DRAM in order to realize the SOC (system on chip) with reduced costs. In the DRAM, a memory array unit comprising a large number of memory cells occupies a large portion of a memory area. Therefore, in order to realize a consolidated DRAM which is more integrated, it is important to reduce an area of the memory cell itself. The memory cell is provided with a memory-cell transistor and a memory capacitor comprising an insulation film having a high dielectric constant, and it is important to miniaturize the memory capacitor in order to reduce the area of the memory cell.
In the memory cell of the stack type, the miniaturization reduces a surface area of the memory capacitor; however, the capacity of the memory capacitor is secured because an insulation film whose dielectric constant is high is adopted. It is necessary to reduce the thickness of the insulation film as thin as possible in order to increase the capacity of the memory capacitor, which, however, unfavorably increases a tunnel leak current of the insulation film of the capacitor. Further, a storage node is silicided because the miniaturizing process demands a logic compatibility, which, however, becomes a factor responsible for increasing a junction leakage in the storage node.
FIG. 10 schematically shows a retention time dependency of a storage node voltage by the leak current. In “0” data, a tunnel leakage of the insulation film of the capacitor is dominant, and the storage node voltage thereby increases toward a cell plate voltage VCP over time. In “1” data, the storage node voltage is finally reduced toward a substrate bias voltage VBB under the influences of junction and channel leakages of an access transistor.
Assuming that:                a parasitic capacitance per bit line is Cb;        a capacity of a capacitor C is Cs;        a potential difference between a bit-line precharge voltage VBP and a “0” storage node voltage V0 is ΔVDL (ΔVDL=VBP−V0); and        a potential difference ΔVDH between a “1” storage voltage V1 and the bit-line precharge voltage VBP is (ΔVDH=V1−VBP),        
a dimension of a sensing signal ΔVL of the “0” data, and a dimension of a sensing signal ΔVH of the “1” data are respectively expressed as follows.ΔVL=k·ΔVDL=k·(VBP−V0)ΔVH=k·ΔVDH=k·(V1−VBP)k=1/(Cb/CS+1)
The sensing signal ΔVL denotes a potential difference generated between compensating bit lines BL and BL when data in a memory cell MC (“0” or “1”) is read onto the bit line BL during a retention time tp.
It is assumed that a lower-limit value of a differential voltage (V1−VBP) in the “1” storage voltage V1 is V1m, and a lower-limit value of a differential voltage (VBP−V0) in the “0” storage node voltage V0 is V0m. An effective range of the lower-limit value V0m in the “0” storage node voltage V0 extends considerably further in terms of time, while an effective range of the lower-limit value V1m of the “1” storage voltage V1 ends considerably earlier in terms of time. More specifically, an amount of the sensing signal of the “1” data is significantly reduced after the retention time tp has passed because the leak current of the “1” data is relatively large. Therefore, the effective range of the lower-limit value V1m of the “1” storage voltage V1 rate-controls the retention time tp.
As shown in FIG. 11, there is available a method of improving the “1” data retention time (the retention time in the “1” storage voltage V1 is extended) by reducing the bit-line precharge voltage VBP and securing the sensing signal of the “1” data after the retention time has passed. An example of the method is recited in Japanese Patent Laid-Open No. H11-16354 of Japanese Patent Documents.
In this example, the bit-line precharge voltage VBP is set to be lower than the cell plate voltage VCP. The effective range of the lower-limit value V1m of the “1” storage voltage V1 extends considerably further in terms of time, while the effective range of the lower-limit value V0m of the “0” storage node voltage V0 ends considerably earlier in terms of time. More specifically, the effective range of the lower-limit value V0m of the “0” storage node voltage V0 rate-controls the retention time tp.
However, in the conventional technology shown in FIG. 11, while the sensing signal of the “1” data after the elapse of retention time tp can be secured, the sensing signal of the “0” data is contrarily reduced in the manufacturing process of the latest miniaturized embedded DRAM because the tunnel leak current of the insulation film whose dielectric constant is high is remarkably increased. Because the bit-line precharge voltage VBP is set to be lower than the cell plate voltage VCP, the effective range of the lower-limit value V0m of the “0” storage node voltage V0 cannot be extended to such a range that the “0” storage node voltage V0 exceeds the bit-line precharge voltage VBP. Therefore, the effective range of the lower-limit value V0m of the “0” storage node voltage V0 rate-controls the retention time tp.